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ics for consumer electronics ddc-plus-deflection controller sda 9361 data sheet 1998-02-01
edition 1998-02-01 this edition was realized using the software system framemaker a published by siemens ag, bereich halbleiter, marketing-kommunikation, balanstra?e 73, 81541 mnchen ? siemens ag 1998. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. for questions on technology, delivery and prices please contact the semiconductor group offices in germany or the siemens companies and representatives worldwide (see address list). due to technical requirements compo- nents may contain dangerous substanc- es. for information on the types in ques- tion please contact your nearest siemens office, semiconductor group. siemens ag is an approved cecc man- ufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support de- vices or systems must be expressly authorized for such purpose! critical components 1 of the semiconduc- tor group of siemens ag, may only be used in life-support devices or systems 2 with the express written approval of the semiconductor group of siemens ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be endangered.
data classification maximum ratings maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. recommended operating conditions under this conditions the functions given in the circuit description are fulfilled. nominal conditions specify mean values expected over the production spread and are the proposed values for interface and application. if not stated otherwise, nominal values will apply at t a =25c and the nominal supply voltage. characteristics the listed characteristics are ensured over the operating range of the integrated circuit. edition 1998-02-01 published by siemens ag, semiconductor group copyright ? siemens ag 1998. all rights reserved. terms of delivery and right to change design reserved. sda 9361 revision history: current version: 1998-02-01 previous version: 1997-04-07 page (in previous version) page (in current version) subjects (major changes since last revision) 33 35 setup time of input hsync (clext=1) changed from 6 ns to 4 ns 35 37 nom. average and max. stand-by current specified 35 37 specification of charge current pump of pll pin lf is unnecessary
sda 9361 table of contents page semiconductor group 4 1998-02-01 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 1.2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 1.4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 1.5 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 system description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3 reset modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.4 frequency ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.5 i2c-bus control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.1 i2c-bus address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.2 i2c-bus format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 2.5.3 i2c-bus commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 2.5.4 detailed description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5.5 explanation of some control items . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 3.1 recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 3.2 characteristics (assuming recommended operating conditions) . . . . . . . 37 4 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5 waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.1 vd- output voltage, 4/3-crt and 16/9-source . . . . . . . . . . . . . . . . . . . . . . 41 5.2 timing diagram of scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 5.3 power on/off diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.4 standby mode, resn diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5.5 function of h,v protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 6 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
p-mqfp-44-2 semiconductor group 5 1998-02-01 ddc-plus-deflection controller sda 9361 mos type ordering code package sda 9361 Q67107-H5167-A703 p-mqfp-44-2 1 overview 1.1 features ? deflection - protection - 16:9 / 4:3 ? no external clock needed ? f 1 pll and f 2 pll on chip ? i 2 c-bus alignment of all deflection parameters ? all ew-, v- and h- functions ? pw eht compensation ? ph eht compensation ? compensation of h-phase deviation (e.g. caused by white bar) ? upper/lower ew-corner correction separately adjustable ? v-angle correction: vertical frequent linear modulation of h-phase ? v-bow correction: vertical frequent parabolic modulation of h-phase ? three reduced v-scan modes (75 %, 66 %, 50 % v-size) adjustable by only 2 bits ? h-frequent pwm output signal for general purpose ? h- and v-blanking time adjustable ? partial overscan adjustable to hide the cut off control measuring lines in the reducedscan modes ? stop/start of vertical deflection adjustable to fill out the 16/9 screen with different letterbox formats without annoying overscan ? control signal scan as reference for vertical positioning of osd, pip etc. ? vertical noise reduction with memory ? standard and doubled line frequencies for ntsc and pal, muse standard, atv standard, hdtv standard ? self adaptation of v-frequency/number of lines per field between 192 and 680 for each possible line frequency ? protection against eht run away (x-rays protection)
sda 9361 semiconductor group 6 1998-02-01 ? protection against missing v-deflection (crt-protection) ? selectable softstart of the h-output stage ? clock generation on chip ? p-mqfp-44-2 package ? 5 v supply voltage 1.2 general description the sda 9361 is a highly integrated deflection controller for ctv receivers with standard or doubled line and field frequencies. it controls among others an horizontal driver circuit for a flyback line output stage, a dc coupled vertical saw-tooth output stage and an east/ west raster correction circuit. all adjustable output parameters are i 2 c bus controlled. inputs are hsync and vsync. the hsync signal is the reference for the internal clock system which includes the f 1 and f 2 control loops. 1.3 pin configuration figure 1 uep10278 hsync 11 12345678910 33 12 44 32 31 30 29 28 27 26 25 24 23 43 13 42 14 41 15 40 16 39 17 38 18 37 19 36 20 35 21 34 22 selfh1_2 clki x2 sdat v dd(d) ss(d) v x1 sclk scan resn scp e/w v dd(a2) v refp refn v ssa(1) v abl d/a dda(1) v hprot clext fh1_2 test hd pwm f refh v refl v ss(a2) v dd(a3) v refc v ss(a3) v dd(d) v v ss(d) ssd ss(a4) v lf dd(a4) v voffd vprot vd+ vd- vsync 2
sda 9361 semiconductor group 7 1998-02-01 1.4 pin description pin no. symbol type description 1 clki i/ttl input for external clock 2 x1 i reference oscillator input, crystal 3 x2 q reference oscillator output, crystal 4sdatiq i 2 c-bus data 5sclki i 2 c-bus clock 6 resn i/ttl reset input, active low 7 scan q/ttl control signal for vertical positioning of osd, pip etc. 8 scp q blanking signal with h- and color burst component (v-component selectable by i 2 c bus) 9 v dd(d) s digital supply 10 v ss(d) s digital ground 11 vprot i watching external v-output stage (input is the v-saw- tooth from feedback resistor) 12 hprot i watching eht (input is e.g. h-flyback) 13 v dd(a1) s analog supply 14 d/a q output of an i 2 c bus controlled dc voltage 15 abl i input for a beam current dependent signal for stabilization of width, height and h-phase 16 v ss(a1) s analog ground 17 v refn iq ground for v refp , v refh , v refl 18 v refp iq reference voltage for ibeam adc, dac, hprot / vprot thresholds 19 v dd(a2) s analog supply 20 e/w q control signal output for east/west raster correction 21 vd+ q control signal output for dc coupled v-output stage 22 vd- q like vd+ 23 v ss(a2) s analog ground 24 v refl iq reference voltages for e/w-dac, v-dac 25 v refh iq like v refl 26 f 2 i line flyback for h-delay compensation 27 pwm q/ttl control signal output
sda 9361 semiconductor group 8 1998-02-01 1.4 pin description (contd) 1) the external clock mode can not be used with 33.75 khz and 35 khz line frequency. pin no. symbol type description 28 vsync i/ttl v-sync input 29 hd q control signal output for h driver stage 30 test i/ttl switching normal operation (test = l) and test mode (test = h: pins 7, 27, 31, 32, 33, 40, 44 are additional test pins) 31 fh1_2 i/ttl switching between 1f h mode (l) and 2f h mode (h) (pin selfh1_2 = 0) 32 clext i/ttl switching between internal (l) and external clock (h) 1) 33 selfh1_2 i/ttl selection of switching between 1f h mode and 2f h mode selfh1_2 = 0:1f h /2f h selected via pin fh1_2 selfh1_2 = 1:1f h /2f h selected via i 2 c-bus register 00 h , bit d5 34 v dd(a3) s analog supply 35 hsync i hsync input (clext = 1: ttl; clext = 0: analog) 1) 36 v refc i reference voltage for sync adc 37 v ss(a3) s analog ground 38 v dd(d) s digital supply 39 v ss(d) s digital ground 40 ssd i/ttl disables softstart 41 v ss(a4) s analog ground 42 lf iq pll loop filter 43 v dd(a4) s analog supply 44 voffd i/ttl defines default value of voff-bit ( i 2 c-bus register 00 h , bit d7)
sda 9361 semiconductor group 9 1998-02-01 1.5 block diagram figure 2 ueb10277 i 2 c protection start up control h-out v-out ew-corr pwm d/a pw/ph corr pll cll scp scan hprot ssd vprot f 2 sclk sdat voffd selfh1_2 test fh1_2 clext vsync hsync clki lf hd e/w pwm d/a abl refn v refp v refh v refl v refc v x1 x2 vd+ vd-
sda 9361 semiconductor group 10 1998-02-01 2 system description 2.1 functional description the main input signals are hsync with standard or doubled horizontal frequency and vsync with vertical frequencies of 50/100 hz or 60/120 hz. the vsync is processed in a noise reduction circuit to enable synchronization by worse transmission too. the output signals control the horizontal as well as the vertical deflection stages and the east/west raster correction circuit. the h-output signal hd compensates the delays of the line output stage and its phase can be modulated vertical frequent to remove horizontal distortions of vertical raster lines (v-bow, v-angle). time reference is the middle of the front and back edge of the line flyback pulse. a positive hd pulse switches off the line output transistor. maximal h-shift is about 4.5 m s (for 1f h ) or 2.25 m s (for 2f h ). picture tubes with 4:3 or 16:9 aspect ratio can be used by adapting the raster to the aspect ratio of the source signal. the v-output saw-tooth signals vd- and vd+ controls a dc coupled output stage and can be disabled. suitable blanking signals are delivered by the ic. the east/west output signal e/w is a vertical frequent parabola of 4th order, enabling an additional corner correction, separately for the upper and lower part. the pulse width modulated horizontal frequent output signal pwm is for optional use. it can be modulated between 1 and 215 steps. the step width is 4 * t h /864. the output d/a delivers a variable dc signal for general purpose. the picture width and picture height compensation (pw/ph comp) processes the beam current dependent input signal abl with effect to the outputs e/w and vd to keep width and height constant and independent of brightness. the alignment parameter horizontal shift compensation enables to adjust the influence of the input signal abl on the horizontal phase. the selectable start up circuit controls the energy supply of the h-output stage during the receiver's run up time by smooth decreasing the line output transistors switching frequency down to the normal operating value (softstart). hd starts with about double the line frequency and converges within 85 ms to its final value. the high time is kept constant.the normal operating pulse ratio h/l is 45/55. the protection circuit watches an eht reference and the saw-tooth of the vertical output stage. h-output stage is switched off if the eht succeeds a defined threshold or if the v-deflection fails ( refer to page 46 ). hprot: input v i < v2 continuous blanking v i > v1 hd disabled v2 v i < v1 operating range
sda 9361 semiconductor group 11 1998-02-01 vprot: vertical saw-tooth voltage v i < v1 in first half of v-period or v i > v2 in second half: hd disabled the pin scp delivers the composite blanking signal scp. it contains burst ( v b ), h- blanking hbl ( v hbl ) and selectable v-blanking (control bit ssc). the phase and width of the h-blanking period can be varied by i 2 c bus. for the timing following settings are possible: bd = 1 : t bl =0 bd = 0, bse = 0 (default value) : t hbl = t f (h-flyback time) bd = 0, bse = 1(alignment range) : t hbl =(4 * h-blanking-time + 1) / cll : t dbl = (h-shift + 4 * h-blanking-phase -2 * h-blanking-time + 43) / cll ssc = 0 : t bl = t vbl during v-blanking period ssc = 1 : t bl is always t hbl figure 3 bg-pulse width t b 54 / cll delay to hsync t db if clext = l-level: (76-4 * internal-h-sync-phase) / cll if clext = h-level: (38-4 * internal-h-sync-phase) / cll ued10260 input signal hsync b t db t dbl t t bl oh v ohbl v ol v
sda 9361 semiconductor group 12 1998-02-01 2.2 circuit description the hsync is reference for a numeric pll. this pll generates a clock which is phase locked to the incoming horizontal sync pulse and exactly 864 times faster then the horizontal frequency. in order to lock the internal frequency to the external sync signal positive horizontal sync pulses are required ( see figure 4 ). figure 4 incoming signal hsync (clext = 0) pulse width t w for i 2 c-bus bit hswid = 0: 3 m s ... 6.1 m s low fh-range 1.5 m s ... 3.1 m s high fh-range pulse width t w for i 2 c-bus bit hswid = 1: 3 m s ... 8.8 m s low fh-range 1.5 m s ... 4.0 m s high fh-range rise time t r :100 ns minimum (clext = 0) the described input signal is first applied to an a/d converter. conversion takes place with 6 bits and a nominal frequency of 27 mhz. the digital pll uses a low pass filter to obtain defined slopes for further measurements (pal/ntsc applications). in addition the actual high and low level of the signal as well as a threshold value is evaluated and used to calculate the phase error between internal clock and external horizontal sync ued10279 r t hsmax v hsmin v v hspp w t
sda 9361 semiconductor group 13 1998-02-01 pulse. by means of digital pi filtering an increment is gained from this. the pi filter can be set by the i 2 c-bus vcr bit so that the lock-in behavior of the pll is optimal in relation to either the tv or vcr mode. moreover it is possible to adapt the nominal frequency by means of 5 i 2 c-bus bits (incr4..incr0) to different horizontal frequencies. an additional bus bit genmod offers the possibility to use the pll as a frequency generator which frequency is controlled by the incr bits. once an increment has been obtained, either from the pi-filter or the i 2 c bus, it can be used to operate the digital timing oscillator. the dto generates a saw-tooth with a frequency that is proportional to the increment. the saw-tooth is converted into a sinusoidal clock signal by means of sin roms and d/a converters and applied to an analog pll which multiplies the frequency by 2 or 4 (depends on mode 1f h or 2f h ; for detailed explanation see pinning and i 2 c-bus description) and minimizes residual jitter. in this manner the required line locked clock is provided to operate the other functional parts of the circuit. if no hsync is applied to pin 35 the system holds its momentary frequency for 2040 lines and following resets the pll to its nominal frequency. the status bit con indicates the lock state of the pll. the system also provides a stable hs-pulse for internal use. the phase between this internal pulse and the external hsync is adjustable via i 2 c-bus bits hphase. it can be shifted over the range of one tv line. an external clock (clki) can be provided by pin selection (clext = h). the clock frequency has to be 864 * f hsync . the external clock mode can not be used with 33.75 khz and 35 khz line frequency. for effective noise suppression the vsync has to pass a window at first and is then processed in a flywheel logic. the window allows a vsync pulse only after a minimum number of lines from its predecessor and sets an artificial one after a maximum number of lines. the number of h-periods between two subsequent vsyncs is stored and determines (after several checks) the following v-periods (internal synchronization). if incoincidence is detected between internal and external vsync, the system switches after a hysteresis of a defined number of v-periods to external synchronization and the checks are repeated. values which influence shape and amplitude of the output signals are transmitted as reduced binary values to the sda 9361 via i 2 c bus. a cpu which is designed for speed reasons in a pipe line structure calculates in consideration of feedback signals (e.g.abl) values which exactly represent the output signals. these values control after d/a conversion the external deflection and raster correction circuits. the cpu firmware is stored in an internal rom.
sda 9361 semiconductor group 14 1998-02-01 2.3 reset modes the circuit is completely reset at power-on/off ( timing diagram see figure 11 ) or if the pin resn has l-level ( timing diagram see figure 12 ). during standby operation some parts of the circuit are not affected ( timing diagram see figure 12 ): note: power-on-reset and resn = low state are deactivated after ca. 32 cycles of the x1/x2 oscillator clock and ca. 42 cycles of the cll clock. standby state is deactivated after ca. 42 cycles of the cll clock. 1) can only be read after power-on-reset is finished power-on-reset external reset (pin resn = low) standby mode ( i 2 c bit stdby = 1) hd output low low active h-protection inactive inactive inactive v-protection inactive inactive inactive i 2 c interface (sda, scl) tristate tristate ready i 2 c register 01 h ...1c h , 1f h set to default values set to default values set to default values i 2 c register 00 h , 1d h , 1e h , 44 h ...48 h set to default values set to default values not affected status bit ponres set to 1 1) set to 1 1) not affected v refp , v refh . v refl not affected not affected inactive cpu inactive inactive inactive
sda 9361 semiconductor group 15 1998-02-01 2.4 frequency ranges the allowed deviation of all input line frequencies is max. 4.5 %. n l : number of lines per frame i: interlaced ni: non interlaced if nsa = 0 (subaddress 01 h /d5 h ) number of lines per field is selfadaptable between 192 and 680 for each specified h-frequency. 1) only with internal clock generation hvn l 15.625 khz 50 hz 625 i 15.75 khz 60 hz 525 i 31.25 khz 50 hz 100 hz 625 ni / 1250i 625 i 31.5 khz 60 hz 70 hz 120 hz 525 ni / 1050 i 449 ni 525 i 32.4 khz 60 hz 1080 i 33.75 khz 1) 60 hz 1125 i 35 khz 1) 66.7 hz 525 ni
sda 9361 semiconductor group 16 1998-02-01 2.5 i 2 c-bus control 2.5.1 i 2 c-bus address 2.5.2 i 2 c-bus format write: read: reading starts at the last write address n. specification of a subaddress in reading mode is not possible. s: start condition a: acknowledge p: stop condition na: not acknowledge an automatically address increment function is implemented. after switching on the ic, all bits are set to defined states. 1000110 s 1 0 0 0 1 1 0 0 a subaddress a data byte a ***** ap s 1 0 0 0 1 1 0 1 a status byte a data byte n a ***** na p
sda 9361 semiconductor group 17 1998-02-01 2.5.3 i 2 c-bus commands 1) see 2.5.5: explanation of some control items control item sub- addr. d7 d6 d5 d4 d3 d2 d1 d0 allowed range effective range can be disabled by bit default value if disabled unit deflection control 0 00 h see below C C C C C deflection control 1 01 h see below C C C C C vertical shift 02 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C vertical size 03 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C vertical linearity 04 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C vertical s-correction 05 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C vertical eht compensation 1) 06 h b7 b6 b5 b4 b3 b2 b1 b0 0..255 0..255 C C C horizontal size 07 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C pin phase 08 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C pin amp 09 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C upper corner pin correction 0a h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C lower corner pin correction 0b h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C horizontal eht compensation 1) 0c h b7 b6 b5 b4 b3 b2 b1 b0 0..255 0..255 C C C horizontal shift 0d h b6 b5 b4 b3 b2 b1 b0 x -64..63 -64..63 C C 1/cll vertical angle 0e h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C vertical bow 0f h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -128..127 C C C pwm start 10 h b7 b6 b5 b4 b3 b2 b1 b0 0..255 0..215 C C 4/cll d/a 1) 11 h b5 b4 b3 b2 b1 b0 x x -32..31 -32..31 C C C vertical blanking time 1) 12 h x b6 b5 b4 b3 b2 b1 b0 0..127 a) bse = 0 b) lines horizontal blanking time 13 h x x b5 b4 b3 b2 b1 b0 0..63 0..63 bse = 0 h-flyback 4/cll start vertical scan 1) 14 h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 c) sse = 0 9 line horizontal blanking phase 15 h b5 b4 b3 b2 b1 b0 -32..31 -32..31 C C 4/cll vertical scan width 0 1) 15 h b9 b8 0..+3 d) ste = 0 e) 256 lines vertical scan width 1 1) 16 h b7 b6 b5 b4 b3 b2 b1 b0 0..255 d) ste = 0 e) lines guard band 1) 17 h x x b5 b4 b3 b2 b1 b0 0..63 0..63 gbe = 0 3 half lines start reduced scan 1) 18 h x x b5 b4 b3 b2 b1 b0 0..63 0, 2..63 srse = 0 2 line vertical sync control 19 h see below C C C C C min. no. of lines / field 1) 1a h b7 b6 b5 b4 b3 b2 b1 b0 0..255 0..255 C C 2 lines max. no. of lines / field 1) 1b h b7 b6 b5 b4 b3 b2 b1 b0 0..255 0..255 C C 2 lines afc eht compensation 1) 1c h b5 b4 b3 b2 b1 b0 x x -32..31 -32..31 C C C internal pll control 1d h see below C C C C C internal h-sync phase 1e h b7 b6 b5 b4 b3 b2 b1 b0 -128..127 -96..119 C C 4/cll pwm width 1f h b7 b6 b5 b4 b3 b2 b1 b0 0..255 0..215 pwm width=0 15 4/cll universal register 1 45 h see below C C C C C universal register 3 47 h see below C C C C C internal voltage ref control 48 h see below C C C C C
sda 9361 semiconductor group 18 1998-02-01 a) the effective range for vertical blanking time : 16 ... 127 (absolute value) if ste = 0 0 ... 127 (offset value) if ste = 1. b) the "default value if disabled" for vertical blanking time : 21 (absolute value)if ste = 0 8 (offset value)if ste = 1. c) the effective range for start vertical scan: 2 ... 127 (absolute value) if ste = 0 if ste = 1 and nsa = 1 -128 ... 127 (offset value) if ste = 1 and nsa = 0. d) the effective range for vertical scan (total width: 10 bit): 160 ... 684 lines. e) the "default value if disabled" for vertical scan equals the number of lines of the source signal reduced by the control value for start vertical scan . (e.g.: input signal: 262 lines per field; start vertical scan = 8 lines; then (if sse = 1, ste = 0) vertical scan = 262 - 8 = 254 lines. at power on the ram containing the control items is cleared. therefore all data are zero by default (if not otherwise defined) before transferring individual values via i 2 c bus. allowed values out of the effective range are limited, e. g. vertical blanking time = 3 is limited to 16 if ste = 0 (that means a minimum of 16 lines is blanked). there are five bits (srse, bse, sse, ste, gbe) in the deflection control byte 1 for disabling some control items. if one of these bits is "0", the value of the corresponding control item will be ignored and replaced by the value "default value if disabled" in the table above. 2.5.4 detailed description the deflection control byte 0 includes the following bits: voff: vertical off 0: normal vertical output due to control items 1: vertical saw-tooth is switched off, vertical protection is disabled default value depends on pin 44 (voffd) voffd = low: 0 voffd = high: 1 voff stdby 2fh bd rabl vr1 vr0 hde
sda 9361 semiconductor group 19 1998-02-01 stdby: stand-by mode 0: normal operation 1: stand-by mode (all internal clocks are disabled) 2fh: setting of line frequency 0: low range of line frequency (14900 hz ... 17650 hz) 1: high range of line frequency (29800 hz ... 35300 hz) n ote: this bit is dont care if pin selfh1_2 has l-level bd: blanking disable 0: horizontal and vertical blanking enabled 1: horizontal and vertical blanking disabled rabl: abl input range 0: 2 v ... 3 v 1: 0 v ... 4 v vr1 ... vr0: reduction of the vertical size 00: 100 % v-size (16:9 source on 16:9 display) 01: 75 % v-size (16:9 source on 4:3 display) 10: 66 % v-size (two 4:3 sources on 16:9 display) 11: 50 % v-size (two 16:9 sources on 16:9 display) hde: hd enable 0: line is switched off (hd disabled, that is l-level) 1: line is switched on (hd enabled) default value depends on pin 40 (ssd) ssd = low: 0 ssd = high: 1 the deflection control byte 1 includes the following bits: nsa: no self adaptation 0: self adaptation on 1: self adaptation off 0 x nsa ste gbe srse sse bse
sda 9361 semiconductor group 20 1998-02-01 ste: scan time enable 0: control items for vertical scan width 0 and width 1 are disabled 1: control items for vertical scan width 0 and width 1 are enabled gbe: guard band enable 0: control item for guard band is disabled 1: control item for guard band is enabled srse: start reduced scan enable 0: control item for start reduced scan is disabled 1: control item for start reduced scan is enabled sse: start scan enable 0: control item for start vertical scan is disabled 1: control item for start vertical scan is enabled bse: blanking select enable 0: control items for blanking times are disabled 1: control items for blanking times are enabled the vertical sync control byte includes the following bits: ssc: sandcastle without vbl 0: output scp with vbl component 1: output scp without vbl component nr: noise reduction 0: no noise reduction of the vertical sync 1: noise reduction of the vertical sync ni: non interlace 0: interlace depends on source 1: no interlace x x ssc nr ni nl2 nl1 nl0
sda 9361 semiconductor group 21 1998-02-01 nl2 ... nl0: number of lines per field when nr = 1 and no vertical sync at the input is detected the internal pll control byte includes the following bits: hswid: maximum width of hsync 0: 6.1 m s for low fh-range 3.1 m s for high fh-range 1: 8.8 m s for low fh-range 4.0 m s for high fh-range genmod: clock generator mode 0: normal pll mode 1: generator mode (fixed frequency output, controlled by incr..) vcr: pll filter optimized for 0: tv mode 1: vcr mode incr4 ... 0: nominal pll output frequency for low fh-range: incr = int((fh * 110592) / fq - 64.625) for high fh-range: incr = int((fh * 55296) / fq - 64.625) (for typical values see table below) nl2 nl1 nl0 number of lines per field 0 0 0 262.5 0 0 1 312.5 0 1 0 525 0 1 1 562.5 1 x x 625 hswid genmod vcr incr4 incr3 incr2 incr1 incr0
sda 9361 semiconductor group 22 1998-02-01 specified range for: genmod = 0: 6 incr 14 genmod = 1: 3 incr 18 (fq = 24.576 mhz) default value: incr = 6 warning: 1)a change of incr or 2fh causes spontaneous changes of the generated clock frequency greater than the specified 4.5 %. switching from pll mode to generator mode (genmod) with constant incr values does not result in exceeding the specified frequency deviation range. 2)if pin ssd has h-level the output signal hd starts immediately after power on. in this case the starting horizontal frequency is either 15.75 khz (if selfh1_2 has h-level or if selfh1_2 and fh1_2 have l-level) or 31.5 khz (if selfh1_2 has l-level and fh1_2 h-level). starting with muse or macintosh standard requires l-level at ssd so that incr can be changed before enabling hd with hde = 1. 3)using external clock at pin 1, clki, (pin 32, clext = 1): no internal protection against missing clock pulses is provided. 4)in order to guarantee error free operation of the build in soft start circuit the input frequency has to be inside the lock range of the pll (+/-4.5 % of standard input frequency) application fh[hz] incr pal 15625 6 ntsc 15750 6 pal (100 hz) 31250 6 ntsc (120 hz) 31500 6 atv 32400 8 muse 33750 11 macintosh 35000 14
sda 9361 semiconductor group 23 1998-02-01 the universal register 1 (subaddress 45 h ) includes the following bit: noisyvcr: handling of noisy input signals in vcr mode 0: normal handling 1: improved handling note: this bit is dont care if bit vcr = 0 (tv mode) the universal register 3 (subaddress 47 h ) includes the following bits: kill_zip: top flutter suppression 0: no top flutter suppression 1: top flutter suppression (phase jumps max. 12 m s for low fh-range rsp. max. 6 m s for high fh-range) tc_3rd: third time constant 0: slow vcr time constant 1: fast vcr time constant note: this bit is dont care if bit vcr = 0 (tv mode) the internal voltage ref. control byte includes the following bits: bandg4 ... adjustment of internal bandgap reference bandg0: 10000: reference output voltage min : 01111: reference output voltage max typical adjustment range is 0.5 v. bandgoff: bandgap off 0: v refh , v refl derived internally from v refp 0 0 noisy vcr 00000 0 0 0 kill_zip tc_3rd 0 0 0 bandg4 bandg3 bandg2 bandg1 bandg0 bandg off bandg4 off 0
sda 9361 semiconductor group 24 1998-02-01 1: external references on v refp , v refh , v refl have to be applied (in this case bandg4off must be = 1) bandg4off: bandgap 4 v off 0: internal bandgap reference is used for v refp 1: external reference on v refp (4 v) has to be applied the status byte includes the following bits: hpon: protection on 0: normal operation of the line output stage 1: high level on input hprot has switched off the line vpon: v-protection on 0: normal operation of the vertical output stage 1: incorrect signal on input vprot has switched off the line con: coincidence not 0: h-coincidence detected 1: no h-coincidence detected ponres: power-on-reset 0: after bus master has read the status byte 1: after each detected reset note: ponres is reset after this byte has been read. 2.5.5 explanation of some control items d/a this item controls directly a 6 bit d/a converter at the output d/a that can be used for general purpose. start vertical scan if enabled (sse = 1) this control item defines the start of calculation of the vertical saw- tooth, the east/west parabola and the vertical function required for the vertical modulated output hd. hpon vpon con - - - - ponres
sda 9361 semiconductor group 25 1998-02-01 vertical scan (width0 and width1) the total width of this control item is 10 bit. therefore two registers (width0 and width1) are necessary. if enabled (ste = 1) it defines the duration of the vertical scan. when the vertical period has more lines than the sum of start vertical scan and vertical scan , the calculation of the vertical saw-tooth, the east/west parabola and the vertical parabola required for hd stops so that the corresponding output signals remain unchanged till the next vertical synchron pulse. guard band this control item is useful for optimizing self adaptation. video signals with different number of lines in consecutive fields (e. g. vcr search mode) must not start the procedure of self adaptation. but switching between different tv standards has to change the slope of the vertical saw-tooth getting always the same amplitude (self adaptation). to avoid problems with flicker free tv systems which have alternating number of lines per field an average value of four consecutive fields is calculated. if the deviation of these average values (e.g. pal: 312.5 lines or 625 half lines) is less or equals guard band , no adaptation takes place. when it exceeds guard band , the vertical slope will be changed. start reduced scan if enabled (srse = 1) this item defines the start of the d/a conversion of the calculated vertical saw-tooth. from begin of the vertical flyback to the line defined by start reduced scan the output signals vd+, vd- remain unchanged (flyback level). other outputs are not affected. a) control bits vr1, vr0 # 00 (reduction of vertical size) in this case the byte is useful for e.g. displaying 16/9 source format on 4/3 picture tubes without visible rgb lines generated of the automatic cut-off control (partial overscan). it defines the start of the reduced amplitude (factors 0.5, 0.66, 0.75) of the vertical saw-tooth ( refer page 39 ). when start reduced scan = 0 the reduction takes place over all lines including vertical flyback. b) control bits vr1, vr0 = 00 (no reduction of vertical size) if start reduced scan > start vertical scan the d/a conversion of the saw-tooth starts ( start reduced scan - start vertical scan ) lines after begin of the calculation. this causes a jump of the output voltage vd+, vd- from flyback to scan level. it may be useful to hide the automatic cut-off control lines if no overscan is desired (e.g. for vga display). if start reduced scan <= start vertical scan this byte has no effect.
sda 9361 semiconductor group 26 1998-02-01 vertical eht compensation this item controls the influence of the beam current dependent input signal abl on the outputs vd+ and vd- according to the following equation: (if rabl = 0) (if rabl = 1) d v vdpp : variation of vd+ and vd- peak-to-peak voltage d v abl : variation of abl input voltage 1) the factor 0.57 depends on v refp , v refh , v refl if vertical eht compensation = 0 the outputs vd+ and vd- are independent of the input signal abl. horizontal eht compensation this item controls the influence of the input signal abl on the output e/w according to the following equation: (if rabl = 0) (if rabl = 1) d v ew : variation of e/w output voltage d v abl : variation of abl input voltage 1) the factor 2.12 depends on v refp , v refh , v refl if horizontal eht compensation = 0 the output e/w is independent of the input signal abl. afc eht compensation deviation of the horizontal phase caused by high beam current (e.g. white bar) can be eliminated by this control item. the beam current dependent input signal abl is multiplied by afc eht compensation . d v vdpp d v abl * vertical eht compensation 512 ------------------------------------------------------------------------ * 0,57 1 ) = d v vdpp d v abl * vertical eht compensation 2048 ------------------------------------------------------------------------ * 0,57 1 ) = d v ew d v abl * horizontal eht com pensation 128 ---------------------------------------------------------------------------------- * 2,12 1 ) = d v ew d v abl * horizontal eht com pensation 512 ---------------------------------------------------------------------------------- * 2,12 1 ) =
sda 9361 semiconductor group 27 1998-02-01 additional to the control items vertical angle, vertical bow and horizontal shift, this product influences the horizontal phase at the output hd according to the following equation: (if rabl = 0) (if rabl = 1) df :variation of horizontal phase at the output hd (positive values: shift left, negatives values: shift right) d v abl :variation of abl input voltage (units: volt) cll :864 * f h 1) the factor 52 depends on v refp vertical blanking time (vbt) vbt defines the vertical blanking pulse vbl which is part of the output signal scp. vbl is synchronized with the leading edge of hsync. it always starts and stops at the beginning of line and never in the center. a) case of ste = 0 in this case the control item vertical blanking time defines the duration of the v-blanking pulse (vbl) exactly in number of lines. because of ic internal limitations 16 through 127 lines can be blanked. if bse = 0 the control item vertical blanking time is disabled and always 21 lines (default value if disabled) are blanked. after power on the control bit bse is 0. therefore 21 lines will be blanked before any programming of the ic. if vertical blanking time is less or equals 21 lines, vbl starts (point a in fig. above) always 0 ... 0.5 line (new odd field) or 0.5 ... 1 line (new even field) prior to the vertical flyback. otherwise vbl is concentric to a fictitious vertical flyback period of 21 lines, that means vbl starts (vbt - 21) / 2 lines at the end of an odd field or (vbt - 20) / 2 at the end of an even field prior to point a. possible start points are only the beginning of line. df d v abl * afc eht compensation 64 ---------------------------------------------------------------- * 52 1 ) cll ----------- = df d v abl * afc eht compensation 256 ---------------------------------------------------------------- * 52 1 ) cll ----------- =
sda 9361 semiconductor group 28 1998-02-01 figure 5 vertical blanking pulse vbl when ste = 0 and number of lines per ued10261 1 ~ ~ 2 141516171819202122232425 hsync ~ ~ vsync vd- vbl (bse = 0) (bse = 1, vbl vbt = 16) (bse = 1, vbt = 25) vbl vbt = 26) (bse = 1, vbl 1 line start of even field start of odd field 21 lines 16 lines 2 lines 25 lines 3 lines 26 lines a ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 2 lines
sda 9361 semiconductor group 29 1998-02-01 field = constant b) case of ste = 1 in this case the control item vertical blanking time is an extension for the v-blanking pulse. - if bse = 1 and vbt = 0 the v-blanking pulse has its minimum: it starts always at end of scan (line b in fig. below) and ends at start of scan (line c) defined by the control items start vertical scan (if sse = 1) and vertical scan . - bse = 1 and (128 > vbt > 0) extend the v-blanking pulse according to the following relationship (if vbt > 127 this value is ignored and replaced by vbt - 128): vbl starts vbt / 2 lines (even field) respectively (vbt + 1) / 2 lines (odd field) prior to line b. vbl ends (vbt + 1) / 2 lines (even field) respectively vbt / 2 lines (odd field) after end of line c. possible start points are only the beginning of line. - if bse = 0 (after power on) the control item vertical blanking time is disabled and vbl starts 4 lines prior to end of scan (line b) and ends 4 lines after start of scan (line c). figure 6 vertical blanking pulse vbl when ste = 1 ued10262 ~ ~ b123c hsync ~ ~ vsync vd- vbl (bse = 0) (bse = 1, vbl vbt = 0) vbt = 7) (bse = 1, vbl 1 line start of even field start of odd field 3 lines ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ 4 lines 3 lines 4 lines even bc
sda 9361 semiconductor group 30 1998-02-01 minimum number of lines per field it defines the minimum number of lines per field for the vertical synchronisation. if the tv standard at the inputs vsync and hsync has less lines per field than defined by minimum number of lines per field no synchronisation is possible.the relationship between minimum number of lines per field and the minimum number of lines is given in the following table: maximum number of lines per field it defines the maximum number of lines per field for the vertical synchronisation. if the tv standard at the inputs vsync and hsync has more lines per field than defined by maximum number of lines per field no synchronisation is possible. the relationship between maximum number of lines per field and the maximum number of lines is given in the following table: minimum number of lines per field minimum number of lines per field 0192 1194 ... ... 127 446 128 448 ... ... 254 700 255 702 maximum number of lines per field maximum number of lines per field 0702 1192 2194 ... ... 127 444 128 446 ... ... 255 700
sda 9361 semiconductor group 31 1998-02-01 most important v-deflection modes for 4:3 crt mode description characteristics notes vr1 vr0 nsa srse gbe ste sse n0 normal mode (for 4:3 source, letterbox) with default settings self adaptation scan start = line 9 start of v-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines mode after power on 0000000 n1 normal mode (for 4:3 source, letterbox) with user defined values self adaptation scan start = start vertical scan if ( start reduced scan > start vertical scan ) start of v-ramp = start reduced scan else start of v-ramp = start vertical scan scan time: depends on source signal guard band = guard band /2 [lines] start of scan adjustable start of v-ramp adjustable guard band adjustable 0001101 s0 shrink mode 75% (for 16:9 source) with default settings self adaptation scan start = line 9 start of reduced v-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines 0100000 s1 shrink mode 75% (for 16:9 source) with user defined values self adaptation scan start = start vertical scan if ( start reduced scan > start vertical scan ) start of reduced v-ramp = start reduced scan else start of reduced v-ramp = start vertical scan scan time: depends on source signal guard band = guard band /2 [lines] start of scan adjustable start of reduced v-ramp adjustable guard band adjustable 0101101
sda 9361 semiconductor group 32 1998-02-01 most important v-deflection modes for 16:9 crt mode description characteristics notes vr1 vr0 nsa srse gbe ste sse n0 normal mode (for 16:9 or 4:3 source) with default settings self adaptation scan start = line 9 start of v-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines mode after power on 0000000 n1 normal mode (for 16:9 or 4:3 source) with user defined values self adaptation scan start = start vertical scan if ( start reduced scan > start vertical scan ) start of v-ramp = start reduced scan else start of v-ramp = start vertical scan scan time: depends on source signal guard band = guard band /2 [lines] start of scan adjustable start of v-ramp adjustable guard band adjustable 0001101 z zoom mode (for 4:3 source, letterbox) scan start = (number_of_lines - vertical scan )/2 + 8 scan time = vertical scan vertical scan controls zoom factor 000 xx1 0 sc scroll mode (for 4:3 source, letterbox) scan start = (number_of_lines - vertical scan )/2 + 8 + start vertical scan scan time = vertical scan like above; start vertical scan can be additionally used for adjustment of picture phase 000 xx1 1 m manual mode (for 4:3 source, letterbox) scan start = start vertical scan scan time = vertical scan scan start and scan time are separately adjustable 001 xx1 x s2 shrink mode 66% (for two 4:3 sources) with default settings self adaptation scan start = line 9 start of reduced v-ramp = line 9 scan time: depends on source signal guard band =1.5 lines 1000000 s3 shrink mode 50% (for two 16:9 sources) with default settings self adaptation scan start = line 9 start of reduced v-ramp = line 9 scan time: depends on source signal guard band = 1.5 lines 1100000
sda 9361 semiconductor group 33 1998-02-01 3 absolute maximum ratings note : absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions or at any other condition beyond those indicated in the operational sections of this specification is not implied. 1) between any internally non-connected supply pin of the same kind. all v dd(d) -and v dd(a) - pins are connected internally by about 3 w the v ss(d) -pins are connected internally by about 3 w parameter symbol limit values unit remark min. max. operating temperature t a -20 70 c storage temperature t stg -40 125 c junction temperature t j 125 c soldering temperature t s 260 c input voltage v i v ss - 0.3 v v dd + 0.3 v output voltage v q v ss - 0.3 v v dd + 0.3 v supply voltages v dd -0.3 6 v supply total voltage differentials -0.25 0.25 v 1) total power dissipation p tot 0.85 w latch-up protection -100 100 ma all inputs/outputs
sda 9361 semiconductor group 34 1998-02-01 3.1 recommended operating conditions parameter symbol limit values unit remark min. nom. max. supply voltages v dd 4.5 5 5.5 v ambient temperature t a -20 25 70 c for analog parameters: 0c ttl inputs: clki, vsync, test, fh1_2, selfh1_2, clext, ssd, voffd, resn h-input voltage v ih 2.0 v dd v l-input voltage v il 0 0.8 v i nput vprot threshold v1 1.4 1.5 1.6 v v refp =4v threshold v2 0.9 1.0 1.1 v v refp =4v input hprot threshold v1 3.9 4 4.1 v v refp =4v threshold v2 2.1 2.4 2.7 v v refp =4v input abl l-input voltage v il 2v v refp =4v rabl = 0 0v v refp =4v rabl=1 full range input voltage 3v v refp =4v rabl = 0 4v v refp =4v rabl=1 reference voltage input pins (internal voltage ref. control byte reg 48h = 00000110) v refp input voltage v vrefp 4v v refh input voltage v vrefh 2.5 v v refl input voltage v vrefl 1.2 v v refn input voltage v vrefn 0v v refc input voltage v vrefc 5 v independent of register 48 h , max = v dd
sda 9361 semiconductor group 35 1998-02-01 3.1 recommended operating conditions (contd) parameter symbol limit values unit remark min. nom. max. input f 2 l-input voltage v il 0 0.7 v v refp =4v h-input voltage v ih 2.0 v dd v v refp =4v input hsync (clext = 0) input voltage range v hspp 2 v dd v see page 12 input voltage low level v hsmin 0 v see page 12 input voltage high level v hsmax v dd see page 12 pulse width (hswid = 0) t w 3.0 6.1 m s low fh-range 1.5 3.1 m s high fh-range pulse width (hswid = 1) t w 3.0 8.8 m s low fh-range 1.5 4.0 s high fh-range rise time t r 100 ns input hsync (clext = 1) l-input voltage v il 0 0.8 v h-input voltage v ih 2.0 v dd v setup time t su 4 ns referred to falling edge of clki hold time t h 12 ns referred to falling edge of clki input vsync pulse width high 100 100/ f h ns fh1_2 = 1, ni = 0 pulse width high 200 100/ f h ns fh1_2 = 0, ni = 0 pulse width high 1.5/ f h 100/ f h ni = 1
sda 9361 semiconductor group 36 1998-02-01 3.1 recommended operating conditions (contd) parameter symbol limit values unit remark min. nom. max. i nput clki (external clock generation, clext = high) input frequency f i 12.5 13.5 15 mhz low fh-range 25 27 30 mhz high fh-range quartz oscillator input / output x1, x2 crystal frequency 24.576 mhz fundamental crystal type, e.g. saronix 9922 520 00282 crystal resonant impedance 40 w external capacitance 27 pf see application information i 2 c bus (all values are referred to min.( v ih ) and max.( v il ) high-level input voltage v ih 3 v dd v low-level input voltage v il 0 1.5 v sclk clock frequency f sclk 0 400 khz rise times of sclk, sdat t r 0.3 m s f sclk = 400 khz fall times of sclk, sdat t f 0.3 m s set-up time data t su;dat 100 ns hold time data t hd;dat 0ns load capacitance c l 400 pf
sda 9361 semiconductor group 37 1998-02-01 3.2 characteristics (assuming recommended operating conditions) parameter symbol limit values unit remark min. nom. max. average supply current i cc 90 150 ma stand-by supply current 25 ma output pins: scan, pwm output low level v ol 0.4 v i o =1ma output high level v oh 2.8 v i o =-1ma input / output sdat output low level v ol 0.6 v i o =6ma output scp output low level v ol 01v i o =1ma output hbl level v ohbl v dd /2 -0.4 v v dd /2 v dd /2 +0.4 v | i o | = 100 m a output high level v oh 4.0 v dd v i o =-1ma dac output d/a dac resolution 6 bit dac output low 1 v v refp =4v dac output high 3.953 v v refp =4v load capacitance c l 30 pf output load 20 k w offset error -3 % 3 % v refp =4v gain error -3 % 3 % v refp =4v inl -1 1 lsb dnl -0.5 0.5 lsb dac output e/w dac resolution 10 bit linear range: 100 ... 900 dac output low 1.45 v input data = 100 1)
sda 9361 semiconductor group 38 1998-02-01 3.2 characteristics (assuming recommended operating conditions) (contd) parameter symbol limit values unit remark min. nom. max. dac output high 3.48 v input data = 900 1) load capacitance c l 30 pf output load 20 k w zero error -2 % 2 % dac output voltage = 2.5 v 2) gain error -5 % 5 % 2) inl -0.2 % 0.2 % 2) dnl -0.1 % 0.1 % 2) 1) v refh = 2.5 v, v refl = 1.2 v 2) v refh = 2.5 v, v refl = 1.2 v, input range = 100 ... 900 dac output vd+, vd- dac resolution 14 bit linear range: 1500 ... 15000 dac output low (vd-) 1.44 v input data = 1500 1) dac output high (vd-) 3.58 v input data = 15000 1) dac output low (vd-) - (vd+) -2.12 v input data = 1500 1) dac output high (vd-) - (vd+) 2.16 v input data = 15000 1) load capacitance c l 30 pf output load 20 k w zero error -1 % 1 % (vd-) - (vd+) = 0 v 2) gain error -5 % 5 % 2) inl -0.5 % 0.5 % 2) dnl monotonous guaranteed by design 1) v refh = 2.5 v, v refl = 1.2 v 2) v refh = 2.5 v, v refl = 1.2 v, input range = 1500 ... 15000
sda 9361 semiconductor group 39 1998-02-01 3.2 characteristics (assuming recommended operating conditions) (contd) parameter symbol limit values unit remark min. nom. max. reference output v refp (adjustable by reg 48 h , bit d7 ... d3) ( reg 48 h , bit d2 = 0, bit d1 = 0) output voltage min 4.0 v bit d7 ... d3 = 10000 output voltage max 4.0 v bit d7 ... d3 = 01111 output current i q -50 0 m a reference output v refh (reg 48 h , bit d2 = 0) output voltage v q 2.4 2.5 2.6 v v refp =4v reference output v refl (reg 48 h , bit d2 = 0) output voltage v q 1.1 1.2 1.3 v v refp =4v output hd output low level v ol 01v i o =8ma output high level v oh v dd -1 v v dd i o =-8ma
sda 9361 semiconductor group 40 1998-02-01 4 application information figure 7 ues10280 source sel synch sep nvm tv contr. sda 9361 2 c i 24.576 mhz 27 pf 27 pf x1 x2 vsync hsync lf + h-coil v b eht abl hd e/w + v-coil vprot vd- vd+ scp scan vprot hprot f 2 + _ resn pwm d/a abl
sda 9361 semiconductor group 41 1998-02-01 5 waveforms 5.1 vd- output voltage, 4/3-crt and 16/9-source figure 8 ued10264 vd- v 0(max) v 0(min) v (line no.) z n srs 263 0 1 2 v v 16/9 2 1 4/3 = v v 2 1 v v 16/9 0.75 srse = 1 start reduced scan (srs) selectable (line 0, 2...63)
sda 9361 semiconductor group 42 1998-02-01 5.2 timing diagram of scan figure 9 timing diagram of scan if ste = 0 ued10281 123 8 ~ ~ ~ ~ 9 10111213141516171819202122 3 2 1 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 ~ ~ ~ ~ hsync (odd field) (even field) hsync d0 2 (internal) * fh vsync ~ ~ 21 lines vbl (bse = 0) 1 line (sse = 0) vd- ~ ~ ~ ~ (sse = 0) scan appr. 8.5 lines (sse = 1, vd- ~ ~ appr. 0.5 lines scan = 12) start vert. appr. 11.5 lines (sse = 1, scan ~ ~ start vert. scan = 12) start of scan appr. 1 line + d0 start of scan
sda 9361 semiconductor group 43 1998-02-01 figure 10 timing diagram of scan if ste = 1 ued10282 123 ~ ~ ~ ~ 3 2 1 ~ ~ ~ ~ hsync (odd field) (even field) hsync d0 2 (internal) * fh vsync ~ ~ vbl (bse = 0) 1 line vd- ~ ~ appr. 0.5 line + d0 scan ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ end of scan ~ ~ start of scan ~ ~ ~ ~ 4 lines 5.5 lines appr. 1 line + d0
sda 9361 semiconductor group 44 1998-02-01 5.3 power on/off diagram figure 11 ued10283 , v refh programmable ~ 42 cycles for low fh-range this time has to be multiplied by 2 power on 1) default c reg. active inactive cpu h cll 01 h 1c ... h 1f , active inactive , 44 48 2 i h ... c reg. 00 h 2 i 1d , h h 1e , h protection refl v de- fault glitch power off programmable ~ 42 cycles default programmable de- fault programmable fault de- fault de- ssd = 1: ~ 380 ssd = 0: ~ 250 c registers 01 tristate refp v , c bus 2 i hd i 2 x1, x2 on- reset power- cycles 32 voltage supply ssd = 1: ~ 380 ssd = 0: ~ 250 m s 1) 1f programmable ready 1c ... h , h tri- state h 1) m s cycles 32 s m 1) h programmable ready c registers 01 i 2 h 1c ... tristate h ,1f s m 1)
sda 9361 semiconductor group 45 1998-02-01 5.4 standby mode, resn diagram figure 12 ued10284 active refl ready default values programmable standby mode for low fh-range this time has to be multiplied by 2 1) 1e h h , h , ... 44 h 48 c reg. i 00 2 1d h inactive programmable 2 c bus i c reg. ... 01 h i 2 1c h 1f , h protection default values external reset values default programmable tristate programmable programmable ready free run hd 2-loop f active inactive active inactive cpu v refp refh v v , , resn standby 32 x 1 cycles 2-loop f ~ 42 cll cycles run ~ 42 cll cycles ssd = 0: ~ 250 ssd = 1: ~ 380 m m 1) s free 1) s
sda 9361 semiconductor group 46 1998-02-01 5.5 function of h,v protection t 0 =2/ f v ... 3 / f v t 1 =64/ f v ... 128 / f v t 2 =1/ f v ... 2 / f v 1) depends on i 2 c-control items 2) hpon or vpon = 1:hd = 0 (off) hprot vprot mode scp hpon 2) i 2 c bus vpon 2) i 2 c bus 1 start up continuous blanking 00 2 h, v operation 1) 00 3 eht over- voltage continuous blanking after t 2 1 after t 2 0 4 h operation v short failure continuous blanking after t 0 if ssc = 0 00 5 v longer failure h off after t 1 continuous blanking after t 0 if ssc = 0 0 1 after t 1 6 eht short over- voltage continuous blanking after t 2 1 after t 2 1 after t 1 v1 v2 or v1 v2 or or 0 t 1 t t _ < < or or 1 t t < or 1 t t <
sda 9361 semiconductor group 47 1998-02-01 6 package outlines figure 13 index marking does not include plastic or metal protrusions of 0.25 max per side gpm05622 0.8 0.3 +0.15 8 c 0.1 0.2 m a-b d c 44x 0.25 min. 2 +0.1 -0.05 2.45 max. d 10 1) d a-b 0.2 h 4x 13.2 d a-b 0.2 44x b 1) 10 13.2 a 44 1 0.6 x 45? h 0.88 0.15 +0.08 -0.02 0.15 7? max. 1) p-mqfp-44-2 (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. smd = surface mounted device dimensions in mm

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